The present invention relates to a circuit and method for testing a nonvolatile semiconductor memory (especially, flash EEPROM), a nonvolatile semiconductor memory including the test circuit and a method for fabricating a memory of that type.
A nonvolatile semiconductor memory (e.g., flash memory) is a device for retaining particular data thereon for a long period, and included in various consumer electronic appliances like cell phones and personal computers, necessary for our daily life. Since a nonvolatile memory is used for a long time, e.g., for ten years, a reliability test has to be carried out thereon to check its data retainability. Actually, though, it is difficult to carry out a reliability test over such a long time. Thus, it is important to develop a circuit and method for evaluating the reliability of a nonvolatile semiconductor memory more easily and more accurately in a shorter time.
Particularly in recent years, a nonvolatile semiconductor memory with a greater storage capacity has been in demand and the test time required has been on the rise disadvantageously. Therefore, the reliability evaluating method should be further improved. Normally, a reliability tester is directly mounted on a wafer where devices under test are disposed, which makes it easier to measure any characteristic of interest.
Examples of the characteristics measured in a reliability test include the threshold voltage of a flash memory cell. The threshold voltage of a flash memory cell is controlled by a quantity of charge existing in the floating gate of the cell, and is a function directly determined by the quantity of charge stored on the particular cell. Thus, the threshold voltage is generally considered the most important parameter determining the state of data stored on a memory cell.
A cell in a memory array may unintentionally gain or lose charge during its operation. This unintentional charge gain or loss may alter the state of data stored on the cell and might deteriorate the resultant device performance. Moreover, any variation occurring during the fabrication process of a memory array, e.g., the size or thickness of the floating gate, thickness of the gate oxide film, and source/drain structure, may change the charge retention characteristic of the floating gate in one of multiple cells included in the memory array. In that case, the device performance may also deteriorate.
However, in evaluating the reliability of an actual large-scale memory, a huge number of cells included in the memory each have to be tested, thus requiring a tremendously long test time and an amazingly high cost. For that reason, a tester, which can accurately control the charge distribution just as observed in the actual devices and yet can easily measure the resultant distribution, has been in high demand.
As an exemplary circuit of that type, a circuit for sensing the non-variable charge gain and loss of a memory cell was disclosed in Japanese Laid-Open Publication No. 11-177072. The circuit is used for estimating the threshold voltage of a given flash memory cell. The circuit includes a group of memory cells that are connected in parallel with each other as shown in FIG. 7 to estimate a deviation from a target threshold voltage. In the following description, a group of memory cells prepared for testing purposes, like that shown in FIG. 7, will be referred to as a xe2x80x9ctest memory groupxe2x80x9d or simply xe2x80x9cmemory groupxe2x80x9d.
The memory group shown in FIG. 7 consists of a plurality of memory cells 801, 802, 803 and 804 including common source 800A, common drain 800B and common gate 800C. The sources 801A through 804A of these cells are connected to the common source 800A. The drains 801B through 804B of the cells are connected to the common drain 800B. The gates of the cells are connected to the common gate 800C. The cells shown in FIG. 7 are connected in parallel. Accordingly, as the threshold voltage applied to the common gate 800C is gradually increased, the common source 800A and the common drain 800B will be electrically continuous to each other when one of the cells that has the lowest threshold voltage turns ON. This is to say, this parallel connection serves as a tester that reflects the characteristic of the cell with the lowest threshold voltage.
The circuit disclosed in the above-identified publication includes, on the same wafer, two types of memory groups, i.e., n- and p-channel memory groups each having the structure shown in FIG. 7. If these two types of memory groups are disposed in this manner, it is possible to test a cell with the lowest threshold voltage in the n-channel memory group. In addition, it is also possible to estimate how much the threshold voltage of the cell has shifted from the target threshold voltage in the negative direction and how the cell loses its charge. Also, in the p-channel memory group showing a characteristic opposite to that of the n-channel memory group, it is possible to test a cell with the highest threshold voltage. And it is also possible to estimate how much the threshold voltage of the cell has shifted from the target threshold voltage in the positive direction and how the cell gains its charge.
However, the known test circuit has the following drawbacks. Specifically, an actual device is of n- or p-channel type. Therefore, either the n- or p-channel memory group of the circuit has a channel structure different from that of the actual device. Thus, a memory group with a channel structure different from that of the actual device may have to be used in testing the device. This leads to inaccurate threshold voltage estimation. For example, if the actual device has an n-channel structure, the threshold voltage thereof estimated by the p-channel memory group is different from the real threshold voltage of the n-channel device. The highest threshold voltage of a cell in the p-channel memory group does not necessarily reflect the highest threshold voltage of a cell in the n-channel memory group.
Furthermore, in evaluating the charge retention characteristic of a memory cell, the tester may be left in a special (e.g., elevated-temperature) environment in order to shorten the test time. In that case, a memory group with a channel structure different from that of an actual device shows a different characteristic, thus also decreasing the accuracy.
In addition, in a normal memory cell, electrons come and go into/out of a floating gate electrode through a tunnel gate oxide film (which will be herein referred to as a xe2x80x9ctunnel oxide filmxe2x80x9d). An accelerated test is carried out in the special environment to finish the reliability test in a shorter time by artificially creating a state in which electrons are exchanged more easily through the tunnel oxide film. However, in the accelerated test, electrons are also likely exchanged between the floating gate electrode and a control gate electrode through a capacitive insulating film, not just through the tunnel oxide film. Should electrons be exchanged through the capacitive insulating film, the result of the accelerated test would be inaccurate. Accordingly, the accelerated test should preferably be carried out using a tester with such a structure as suppressing the exchange of electrons through the capacitive insulating film.
It is therefore an object of the present invention to provide a circuit and method for accurately evaluating the performance of a memory cell in a flash memory array.
An inventive circuit for testing a nonvolatile semiconductor memory includes a serial connection of flash memory cells as a first memory group. The gates of the flash memory cells have been connected to each other and a first one of the cells has its source or drain connected to the source or drain of a second one of the cells when the first and second cells are adjacent to each other.
In one embodiment of the present invention, the circuit may further include a parallel connection of flash memory cells as a second memory group, in which the sources of the cells have been connected together, the drains of the cells have also been connected together and the gates of the cells have also been connected together.
In this particular embodiment, the serial connection preferably further includes a current amplifier or a voltage amplifier.
In another embodiment, each of the flash memory cells in the serial connection preferably has the same structure as each of the flash memory cells in the parallel connection.
An inventive testing method is a method for testing a nonvolatile semiconductor memory using a test circuit. The method includes the step of a) preparing the test circuit, which includes a serial connection of flash memory cells and a parallel connection of flash memory cells. In the serial connection, the gates of the flash memory cells have been connected to each other and a first one of the cells has its source or drain connected to the source or drain-of a second one of the cells when the first and second cells are adjacent to each other. In the parallel connection, the sources of the cells have been connected together, the drains of the cells have also been connected together and the gates of the cells have also been connected together. The method further includes the step of b) evaluating a characteristic of one of the flash memory cells that has the highest threshold voltage in the serial connection included in the test circuit. And the method further includes the step of c) evaluating a characteristic of one of the flash memory cells that has the lowest threshold voltage in the parallel connection included in the test circuit.
In one embodiment of the present invention, the steps b) and c) may be performed at regular intervals in an environment where loss or injection of retained charges from/into each of the flash memory cells is accelerated.
Specifically, in the environment, each of the flash memory cells belonging to the serial connection may have its threshold voltage set higher than a threshold voltage of the nonvolatile semiconductor memory in an operating range thereof.
Alternatively, in the environment, each of the flash memory cells belonging to the parallel connection may have its threshold voltage set lower than a threshold voltage of the nonvolatile semiconductor memory in an operating range thereof.
As another alternative, in the environment, a voltage, accelerating the loss or injection of the retained charges, may be applied to at least one of the gate, drain, source and substrate of each of the cells belonging to the serial or parallel connection.
Also, the temperature of the environment may be set to a temperature at which the nonvolatile semiconductor memory is tested to accelerate the loss or injection of the retained charges.
An inventive nonvolatile semiconductor memory includes: a circuit for testing the nonvolatile semiconductor memory; and an array of flash memory cells. The circuit includes a serial connection of flash memory cells and a parallel connection of flash memory cells. In the serial connection, the gates of the flash memory cells have been connected to each other and a first one of the cells has its source or drain connected to the source or drain of a second one of the cells when the first and second cells are adjacent to each other. In the parallel connection, the sources of the cells have been connected together, the drains of the cells have also been connected together and the gates of the cells have also been connected together. Each of the flash memory cells in the circuit and each of the flash memory cells in the array include a tunnel insulating film, a floating gate electrode, a capacitive insulating film and a control gate electrode. The capacitive insulating film of each of the flash memory cells in the circuit is thicker than the capacitive insulating film of each of the flash memory cells in the array.
In one embodiment of the present invention, a ratio of the capacitance of the floating gate electrode to the capacitance of the tunnel insulating film in each of the flash memory cells of the array may be equal to a ratio of the capacitance of the floating gate electrode to the capacitance of the tunnel insulating film in each of the flash memory cells of the circuit.
In another embodiment, the channel region of each of the flash memory cells in the array may have the same shape as the channel region of each of the flash memory cells in the circuit.
An inventive method for fabricating a nonvolatile semiconductor memory includes the step of a) defining an isolation region in a semiconductor substrate, thereby defining first and second active regions that are electrically isolated from each other by the isolation region. The method further includes the step of b) forming a tunnel insulating film over the first and second active regions. The method further includes the step of c) forming floating gate electrodes on the tunnel insulating film. The method further includes the step of d) forming a first insulating film over the floating gate electrodes. The method further includes the step of e) selectively removing part of the first insulating film that has been formed over the first active region. The method further includes the step of f) forming a second insulating film over the floating gate electrode in the first active region and over the first insulating film in the second active region. And the method further includes the step of g) forming control gate electrodes over the second insulating film.
In one embodiment of the present invention, at least one of the first and second insulating films may be formed by a CVD process.
An inventive circuit for testing a nonvolatile semiconductor memory includes a serial connection of flash memory cells. Thus, the threshold voltage of a flash memory array can be estimated using a memory group that has the same channel structure as that of an actual device. Accordingly, the circuit can evaluate the performance of each cell in the flash memory array more accurately than a known test circuit. Where the circuit further includes a parallel connection of flash memory cells, it is possible to estimate both a threshold voltage reflecting the highest threshold voltage of one of the cells in the memory array and a threshold voltage reflecting the lowest threshold voltage of one of the cells in the memory array.
Another inventive nonvolatile semiconductor memory includes a test circuit, in which the capacitive insulating film of each of the flash memory cells is thicker than the capacitive insulating film of each of the cells in the flash memory array under test. Thus, electrons are less likely exchanged through the capacitive insulating film in the test circuit. Accordingly, a characteristic of a particular cell (specifically, the charge retention characteristic of a tunnel insulating film) in the flash memory array can be evaluated more accurately.
Thus, according to the present invention, the performance of a particular cell in the flash memory array under test can be evaluated more accurately. As a result, the design and fabrication processes of a nonvolatile semiconductor memory can be improved and optimized more rapidly and more appropriately compared to the prior art. In addition, a highly reliable memory can be developed in a shorter cycle time.